The present invention relates to a semiconductor integrated circuit; and, more particularly, to an electro static discharge (ESD) protection circuit for protecting an internal device from an ESD.
In a semiconductor integrated circuit, as integration is increased, a source-to-drain channel length is decreased, thereby causing unintentional electric phenomena, such as an ESD characteristic deterioration, a hot carrier effect and a punch-through, etc. to occur.
An electrostatic discharge caused by static electricity largely includes two kinds. First is a machine model in which static electricity is caused by unstable connection of a device when the device is equipped with a test device with a package form. In this case, the static electricity has a low voltage of about 250 V, but has small impedance so the amount of electric charge is relatively high. Second is a human body model in which static electricity induced within a human body is discharged when a user touches a device. In this case, the static electricity is discharged at a high voltage of about 2000 V, but has high impedance, so the amount of electric charge is low.
When a MOS device is exposed to a static electricity discharge, a gate oxide rupture and a junction spiking, etc, can be generated so that the device can be entirely demolished or have minute damage with serious effects on its reliability.
In view of the above, an ESD protection circuit is inserted in a coupling region between internal and external circuits of an integrated device to protect it from damage caused by an influx of static electricity. The static electricity is removed by the ESD protection circuit through a ground line and a power line, thereby keeping the internal circuit safe.
The ESD protection circuit is provided with a MOS transistor between a ground and a pad to extract the static electricity toward the ground. A drain region (the pad connection part) of the MOS transistor should have high resistance to achieve enhancement of the ESD characteristic for the following reasons.
First, when the MOS transistors are turned on in the ESD situation, all of the transistors can be equally turned on without turning on specific MOS transistors at both ends of the protection circuit if each drain has an equal resistance.
Second, in the ESD situation, when the MOS transistor enters a snap-back mode, impedance of the drain must be increased in order to make the second breakdown voltage higher than the snap-back voltage, and, by doing so, various transistors can be turned on at the same time.
On the other hand, for a ULSI/VLSI MOS device requiring a high speed operation, a salicide (self-aligned silicide) process is well known as an effective method to obtain a low contact resistance and then this process is practically used.
However, the salicide process deteriorates the ESD characteristics by decreasing the drain resistance of an NMOS transistor in the ESD protection circuit. Also, the thicker the silicide layer is, the weaker the ESD protection is.
In a conventional method, even if the salicide process is applied to the integrated circuit for high speed processing, this process is not applied to a MOS transistor in an ESD protection region. This conventional method is illustrated in U.S. Pat. No. 5,994,176, assigned to Texas Instruments and Acer Incorporated, and issued on Nov. 30, 1999.
FIG. 1 is a cross-sectional view showing the aforementioned conventional method. As shown in FIG. 1, in a transistor 110 in a functional region, silicide layers 113 are formed on a gate electrode 111 and a source/drain region 112. However, in a transistor 150 in an ESD protection region, a silicide layer is not formed on a gate electrode 151 and a source/drain region 152 which are covered with a barrier layer 170.
Likewise, in the conventional method, the functional region and the ESD protection region are divided. The functional region has the salicide layer to obtain characteristic enhancement, such as a high speed operation, etc., and the ESD protection region realizes a ballast resistance which does not apply salicide layers to the MOS transistor for making the ESD protection characteristics better.
However, the conventional method requires an additional process, such as a barrier layer formation, etc., to realize the ESD protection circuit. In this case, a leakage current is generated by such an additional process, and the process is complicated and the unit cost is increased.
A design of a transistor is important to show good characteristics in an ESD protection circuit. It is especially important to prevent the formation of the silicide in the region of the NMOS transistor, passing through a current toward a ground at an ESD situation, during the formation of a semiconductor substrate.
In the fully silicide process that applies the silicide process to a source region, a drain region and a gate electrode of the ESD protection transistor, source/drain regions of the NMOS transistors in a functional region form a little resistance to thereby increase operation speed of a device. However, in such an ESD protection circuit, when an ESD situation is generated, a little resistance of drain regions brings out worse results. Therefore, for good ESD characteristics, a high resistance value of the drain region of the ESD protection transistor is required.
Since the conventional method uses a mask to prevent formation of a silicide in a drain region, the processing steps are complicated and unit price is increased. Also, as a result of the additional process, a leakage current is generated.
In accordance with an aspect of the present invention, an ESD protection circuit is provided comprising an NMOS transistor connected to a ground voltage terminal, the NMOS transistor having a gate electrode, a source region and a drain region, and further including silicide layers on the gate electrode, the source region and the drain region; and a PMOS transistor having a gate electrode connected to a ground voltage terminal, the PMOS transistor connecting the NMOS transistor to a pad.
In accordance with another aspect of the present invention, there is provided an ESD protection circuit comprising a P-type semiconductor substrate; an N-well formed in the P-type semiconductor substrate; an NMOS transistor having an N+ source junction, an N+ drain junction and a gate polysilicon which is in contact with a ground voltage line, wherein the N+ source junction, the N+ drain junction and the gate polysilicon are formed on the P-type semiconductor substrate; a PMOS transistor having a P+ drain junction, a P+ source junction and a gate polysilicon, the PMOS transistor being connected to the N+ source junction of the NMOS transistor, wherein the P+ drain junction, the P+ source junction and the gate polysilicon of the PMOS transistor are formed in the N-well; an N+ junction connected to the P+ source junction of the PMOS transistor and to a pad; and silicide layers formed on each of the gate polysilicon layers, the source and drain junctions of the PMOS and the NMOS transistors, and the N+ junction.
In accordance with yet another aspect of the present invention, there is provided a semiconductor integrated circuit, comprising a pad; an internal circuit for performing a function in response to a signal inputted to the pad and including a plurality of first MOS transistors having silicide layers on gate electrodes and on source and drain junctions; a peripheral circuit having a plurality of second MOS transistors having silicide layers on gate electrodes and on source and drain junctions thereof; and an ESD protection circuit forming a current path between the pad and the internal circuit for protecting the internal circuit from static electricity, wherein the ESD includes: an NMOS transistor connected to a ground voltage line; and a PMOS transistor having a gate electrode connected to the ground voltage line, and connecting the NMOS transistor to the pad.